Selected Projects, Sean Lie
Hardware Support For Transactional Memory
2003-2004: Transactional memory is an architectural mechanism in shared-memory supercomputers designed to give individual processors the ability to perform several memory operations atomically. Transactional memory provides a parallel programming environment that is more intuitive, more fault-tolerant, and higher performance than conventional locking techniques. More InformationAn Integrated Hardware-Software Approach to Transactional Memory
2003: In this paper, I propose an integrated hardware-software implementation of transactional memory. The integrated approach gives us the best of both hardware and software transactions. It allows small and short transactions to run in hardware with very low overhead. In the common case, transactions are small and short so it is desirable to run them fast. On the other hand, large and long transactions run slower in software but are nevertheless possible and fully supported. Moreover, the high overhead is also amortized over the common case and thus does not have a significant penalty on overall performance. More InformationParallel Programming Interfaces
2003: For my final project in 6.338 (Applied Parallel Computing), I am looking at different parallel programming interfaces. Different parallel architectures lend themselves to different programming "styles" or interfaces that the programmer has to work with. For example, OpenMP and MPI are programming interfaces that are generally associated with shared memory and clusters architectures respectively. I will compare some of these interfaces in terms of performance and programming ease. This work is related to my Master's thesis. More InformationBooth Recoded Multiplier
2002: For my final project in 6.371 (Introduction to VLSI Systems), Benjamin Walker, Jeremy Walker and I designed and implemented an 8x8 bit booth recoded multiplier. Logic design, layout and verification were done for three different versions of the multiplier: i) static CMOS, ii) pipelined static CMOS, and iii) dual-rail domino. More InformationMPSA
2002: For a project in 6.033 (Computer System Engineering), I designed a memory system called MPSA (Multiple Permission table in a Single Address space) for a RISC microprocessor. MPSA achieves both memory sharing and isolation in a single address space. MPSA demonstrates that implementing enforced isolation in a single address space does not necessarily entail a complicated system nor does it require significant changes to existing hardware and software structures. More InformationStupid Chicken
2002: I participated in the annual Autonomous Robot Design Competition (6.270) as part of a team with Steven Chan and Buddhika Kottahachchi. The competition was called Chicken and our robot was named Stupid Chicken. We were given one month to design and build a robot with LEGO that would be able to compete against another robot autonomously. Stupid Chicken s strategy was to score a few points very early and block the opponent s goal for the remainder of the match. We received the Organizer s Choice award for this robot. More InformationShadow Ball
2001: For my final project in 6.111 (Introductory Digital Systems Laboratory), Manu Seth, Sourav Dey and I designed and implemented a simple video interaction game called Shadow Ball. Using a video camera and a monitor the user of the system is able to touch a virtual ball and interact with it through his physical motion. The system was designed and implemented from ground up using simple logic chips and CPLDs. We received the 2002 G.C. Newton Jr. Award (for outstanding undergraduate project) for Shadow Ball. More InformationDiaBetNet
2001: I was a student member of the Health Special Interest Human Design research group under Prof. Pentland. I worked with Vikram Kumar on a project called DiaBetNet. DiaBetNet is a diabetes monitoring system for children. It uses wireless portable computing as a means to achieve compliance and community among Type I diabetic children. I developed the first versions of the software and hardware used for preliminary DiaBetNet testing. More Information